This invention relates generally to integrated circuits and, more particularly, to methods for forming capacitors in integrated circuits.
Dynamic random access memory (DRAM) cell is a type of integrated circuits which uses a capacitor. A DRAM cell's capacitor stores a charge which represents data, that is, a logic 1 or logic 0 condition. A DRAM cell also includes a transistor for accessing the capacitor to charge or discharge the capacitor (i.e., "write" new information to the DRAM cell), to determine whether a charge is stored in the capacitor or not (i.e., "read" the information stored in the DRAM cell), or to refresh a charge stored in the capacitor.
DRAM cells are typically organized into arrays of DRAM cells. With the continual increase in integration density of integrated circuits, space available for each DRAM cell in an array is continually reduced. Such reduction can affect the performance of the DRAM cell. For example, the capacitance of a DRAM cell's capacitor may be reduced as the integration density is increased, reducing the data retention time of the cell.
Various methods exist for increasing the capacitance of a DRAM cell's capacitor. Some of these methods entail increasing the surface area of the electrodes of the DRAM cell's capacitor. Referring to FIG. 1, one technique for increasing the surface area of the electrodes involves forming hemispherical silicon grains (HSG) 2 over an electrode 3 of a trench capacitor 4 of a DRAM cell 1. To form the hemispherical silicon grains (HSG), an amorphous silicon layer is deposited over electrode 3. This amorphous silicon layer is then subjected to a two-step anneal process. In the first step, the amorphous silicon layer is annealed in a silane (SiH.sub.4) environment to form small silicon crystal structures on the layer. In the second step, the amorphous silicon layer is annealed in a vacuum to re-crystallize the silicon in the amorphous silicon layer around the small crystal structures to form hemispherical silicon grains (HSG) 2. Preferably, the second step is continued until the entire amorphous silicon layer is re-crystallized. Note that if the amorphous silicon layer is doped, HSG particles are also doped. If the amorphous silicon layer is not doped, then the HSG particles are not doped and should be doped. In that case, the HSG particles can be doped by ex-situ doping by conventional gas plasma doping or plasma doping techniques. The HSG particles can also be doped by out diffusion from another layer, such as from a buried plate.
After forming the hemispherical silicon grains (HSG) 2, a dielectric layer 5 is deposited over the grains. Dielectric layer 5 substantially conforms to the shape of the grains and therefore has an uneven surface. The surface area of the uneven surface of dielectric layer 5 can be two to three times greater than that which would have resulted from depositing dielectric layer 5 over the smooth silicon surface of trench walls 6 of trench capacitor 4. A second electrode 7 is then formed over dielectric layer 5 by filling the trench with doped poly-crystalline silicon. Because of the unevenness of dielectric layer 5, electrode 7 also has an increased electrode surface area. The structure is then processed in a conventional manner to form DRAM cell 1.